Self biased high efficiency fully differential RF rectiier. The rectifier (1) comprises at least one stage having two NMOS transistors (2, 3) with isolated bulks. The source terminal (4) of one transistor 2 is connected to a irst node (5) and the drain terminal (6) of said one transistor is earthed. The substrate terminal (7) of said one transistor is connected to the drain terminal thereof. The source terminal (8) of the other transistor (3) is connected to a second node (9) which is connected to an output terminal (10). The drain terminal (11), substrate terminal (12) and gate terminal (1 3) of the other transistor are connected to the first node. The gate terminal (14) of said one transistor is connected to the second node. The first and second nodes are connected across a RF source(15) through coupling capacitors(16,17), respectively. The transistors are alternatively biased using the node voltage from each other. As a result, no external bias voltage is required. As the rectifier is fully differential, series resistance of the rectification path is reduced thereby increasing the power conversion efficiency of the rectifier (Fig   1).

Indian patent application no. 470/MUM/2012
Inventors: Maryam Shojaei Baghini, Girish Kumar, Mahima Arrawatia, Varish Diddi